The present invention relates to a ferroelectric random access memory (FeRAM) and, more particularly, to a FeRAM having adjacent memory cells sharing cell plate and a driving method for the same.
A ferroelectric random access memory (FeRAM) is a nonvolatile semiconductor memory device with a highly integrated dynamic random access memory (DRAM), the speedy information processing of a static random access memory (SRAM), and the information storing function of a flash memory. As compared with a conventional flash memory and an electrically erasable programmable read only memory (EEPROM), the FeRAM has a relatively low operational voltage and an operating speed that is about 1000 times faster.
When voltage is applied to a DRAM capacitor, which includes a dielectric layer such as a SiO2 layer or a SiON layer, and then the voltage supply is terminated, the charges in the DRAM capacitor are discharged so that data stored in the DRAM are lost.
The ferroelectric material has two stabilized remnant polarization states at room temperature. Unlike the DRAM capacitor, the ferroelectric capacitor in the FeRAM maintains previously stored data by the remnant polarization of a ferroelectric material even if the power supply is terminated.
FIG. 1 is a graph showing a hysteresis loop of a ferroelectric capacitor. In FIG. 1, positive voltage is defined when the potential of a plate line is higher than that of a bit line and the remnant polarizations at points xe2x80x9caxe2x80x9d and xe2x80x9ccxe2x80x9d, are defined to data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, respectively.
If the transistor is turned on and a negative voltage is applied to the plate line xe2x80x9cPLxe2x80x9d, then a negative voltage is also applied to the ferroelectric capacitor and a charge variation passes through point xe2x80x9cdxe2x80x9d in the hysteresis loop. After that, in case of turning the applied voltage to xe2x80x9c0 Vxe2x80x9d, a polarization value goes to point xe2x80x9caxe2x80x9d and the data xe2x80x9c1xe2x80x9d is stored. Meanwhile, when the data xe2x80x9c0xe2x80x9d is inputted, a positive voltage is applied to the ferroelectric capacitor and the charge variation passes through point xe2x80x9cbxe2x80x9d and, turning the applied voltage to xe2x80x9c0 Vxe2x80x9d, then a polarization value goes to point xe2x80x9ccxe2x80x9d and the data xe2x80x9c0xe2x80x9d is stored.
When the voltage is applied to the ferroelectric capacitor, data are written by detecting the voltage variation on the bit line. That is, if positive voltage is applied to the capacitor, in case the data is xe2x80x9c0xe2x80x9d, the charge variation of xcex94Q0 is detected. That is, the charge variation on the bit line is determined by information stored on the capacitor. The charge variation due to the remnant polarization of the ferroelectric capacitor changes a voltage level on the bit line. Typically, parasite capacitance xe2x80x9cCBLxe2x80x9d exists on the bit line itself. When the transistor is turned on and a memory to be read out is selected, charges of as much as xcex94Q1 or xcex94Q0 are outputted. Bit line voltages xe2x80x9cVBL1xe2x80x9d and xe2x80x9cVBL0xe2x80x9d are acquired by dividing the xcex94Q1 and the xcex94Q0 with the sum of bit line capacitance xe2x80x9cCBLxe2x80x9d and ferroelectric capacitor capacitance xe2x80x9cCsxe2x80x9d and is given by:
VBL1=xcex94QBL1/(CBL+Cs)
VBL0=xcex94QBL0/(CBL+Cs)
Therefore, the potential on the bit line is varied according to the difference between the data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d. When the transistor is turned on by applying voltage to the word line, potential on the bit line is changed to the xe2x80x9cVBL1xe2x80x9d or the xe2x80x9cVBL0xe2x80x9d. In order to determine whether the potential on the bit line is in a voltage level of xe2x80x9cVBL1xe2x80x9d or xe2x80x9cVBL0xe2x80x9d, a reference voltage xe2x80x9cVrefxe2x80x9d, which is set to a specific voltage level between the voltage levels xe2x80x9cVBL1xe2x80x9d and xe2x80x9cVBL0xe2x80x9d, is used.
SrBi2Ta2O9 (hereinafter, referred to as an SBT) or Pb(Zr, Ti)O3 (hereinafter, referred to as a PZT) is mainly used as a dielectric material for the FeRAM. The material property of the bottom layer disposed under a ferroelectric layer is important to crystallize the ferroelectric layer. That is, in the ferroelectric capacitor, the characteristic of the ferroelectric layer is largely affected by the electrode, so it is necessary to have sufficiently low resistance, a small lattice mismatch between the ferroelectric material and the electrode, a high heat-resistance, a low reactivity, a high diffusion barrier characteristic and a good adhesion between the electrode and the ferroelectric material.
FIG. 2A is a circuit diagram of a conventional FeRAM having adjacent memory cells of which plate lines are separated. Each transistor Tr1, Tr2, in adjacent memory cells CELL0, CELL1, includes a gate electrode respectively connected to a word line WL0, WL1, a source commonly connected to a bit line BL0 and a drain respectively connected to an electrode of a capacitor C1, C2. Each capacitor C1, C2 includes a first electrode connected to cell plate line CP0, CP1, a second electrode connected to the transistor Tr1, Tr2 and a ferroelectric layer formed between the first electrode and the second electrode. The second electrode of the capacitors C1, C2, respectively connected to the transistors Tr1, Tr2, functions as a charge storage electrode. FIG. 2B is a layout of the FeRAM shown in FIG. 2A.
The driving method of a FeRAM differs from a DRAM. In the case of the DRAM, a word line is selected to operate a memory cell when the voltage of a plate line connected to the memory cell is already fixed to a half of the operating potential Vcc. The voltage of a bit line in the DRAM becomes higher or lower than Vcc/2 according to stored data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d. But, in the case of the FeRAM, the voltage of the cell plate line is varied from xe2x80x9c0 Vxe2x80x9d to the operating potential xe2x80x9cVccxe2x80x9d after a word line is selected.
Also, a sense amplifier of the DRAM compares the voltage of the bit line with the voltage of the bit bar line, of which voltage is fixed to the xe2x80x9cVcc/2xe2x80x9d, and amplifies the voltage difference between the bit line and bit bar line to detect the stored data, whether the stored data is xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. But, the voltage of the bit line in the FeRAM is increased regardless of whether the stored data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. However, the amount of voltage increase depends on the stored data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, such that the voltage increase amount is relatively high when the stored data is xe2x80x9c1xe2x80x9d. Therefore, a reference voltage generator, generating a voltage value between the data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, is needed to provide a reference voltage.
The time for driving a cell plate line increases in proportion to the capacitance of the cell plate line. Therefore, a line shaped cell plate is formed to reduce the capacitance and to increase speed. Also, a method is provided to select and to drive a cell plate line whenever a memory cell is selected.
FIG. 3 is a cross-sectional view of the FeRAM shown in FIG. 2A and the layout shown in FIG. 2B.
A semiconductor substrate 10 including an isolation layer 11 and a transistor having a gate insulating layer (not shown), word lines WL0, WL1 and source/drain 12, is provided. A first interlayer insulating layer 13 is formed over the semiconductor substrate 10, and a capacitor, including a bottom electrode 14, a ferroelectric layer 15 and a top electrode 16, is formed. The bottom electrode 14 is connected to cell plate line CP0, CP1 and the top electrode 16 is connected to a storage node. A second interlayer insulating layer 17 is formed on the resulting structure. A first contact hole exposing the top electrode 16 and a second contact hole exposing the source/drain 12 are formed. A metal diffusion barrier layer 18, an interconnection line 19A connecting the top electrode of the capacitor with one of the source/drain 12 and a bit line plug 19B connecting to the other source/drain, are formed. Thereafter, a third interlayer insulating layer 20 and a bit line BL0, connected to the bit line plug 19B, are formed.
Generally the DRAM has a structure referred to as COB, that is, the capacitor of the DRAM is formed over the bit line. By contrast, the FeRAM has a structure referred to as CUB, that is, the capacitor of the FeRAM is formed under the bit line for the convenience of the fabrication process.
The memory cell size of the DRAM is determined by the design rule 8F2. The xe2x80x9cFxe2x80x9d denotes a minimum feature size and generally represents the width of the gate electrode. In the case of FeRAM, it is difficult to meet the design rule, even if the FeRAM has the CUB structure like the DRAM. The memory cell size of the FeRAM is determined by the size of capacitor. Accordingly, the size of the capacitor should be reduced to diminish the memory cell size.
It is possible to reduce the capacitor size without diminishing the size of the charge storage node by forming adjacent memory cells which share the cell plate.
FIG. 4A is a circuit diagram of a conventional FeRAM in which cell plate is shared by the adjacent memory cells. Each transistor Tr1, Tr2, in adjacent memory cells CELL0, CELL2, includes a gate electrode respectively connected to a word line WL0, WL1, a source commonly connected to a bit line BL0 and a drain respectively connected to an electrode of a capacitor C1, C2. Each capacitor C1, C2 includes a first electrode commonly connected to a cell plate CP0_1, a second electrode respectively connected to the transistor Tr1, Tr2 and a ferroelectric layer formed between the first electrode and the second electrode. The first electrodes of the two capacitors C1, C2 are commonly coupled to the cell plate CP0_1, and the second electrodes of the two capacitors C1, C2, which are respectively connected to the transistors Tr1, Tr2, function as charge storage electrodes. FIG. 4B is a layout of the FeRAM shown in FIG. 4A.
FIG. 5 is a cross-sectional view showing the FeRAM according to the circuit diagram shown in FIG. 4A and the layout shown in FIG. 4B.
A semiconductor substrate 10 including an isolation layer 11 and transistors respectively having a gate insulating layer (not shown), a gate electrode connected to the word line WL0, WL1 and source/drain 12, is provided. A first interlayer insulating layer 13 is formed over the semiconductor substrate 10, and a capacitor, including a bottom electrode 14 connected to the cell plate line CP0_1, a ferroelectric layer 15, and a top electrode 16 connected to a storage node. A second interlayer insulating layer 17 is formed on the resulting structure. A first contact hole exposing the top electrode 19 and a second contact hole exposing the source/drain 12 are formed. A metal diffusion barrier layer 18, an interconnection line 19A connecting the top electrode of the capacitor with one of the source/drain 12 and a bit line plug 19B connecting to the other source/drain, are formed. Thereafter, a third interlayer insulating layer 20 and a bit line BL0, connected to the bit line plug 19B are formed.
The cell size of the FeRAM shown in FIGS. 4A, 4B and 5, may be diminished by the reduction in the capacitor size, because a spacing can be omitted owing to the cell plate line being commonly coupled to the two adjacent memory cells.
However, a data disturbance problem is generated due to the fact that the cell plate line is shared by the two adjacent memory cells. That is, if the word line WL0 is selected to operate cells CELL0, CELL1 connected to the word line WL0, and a voltage is applied to the cell plate line CP0_1 shared by two adjacent memory cells CELL0, CELL1, then the voltage is also applied to the capacitor in the memory cells CELL2, CELL3 sharing the cell plate line CP0_1, even though memory cells CELL2, CELL3 are not connected to the word line WL0.
The junction capacitance of the storage node is much smaller than the capacitance of the ferroelectric capacitor. Accordingly, the voltage applied to the ferroelectric capacitor, in the memory cells CELL2, CELL3 connected to the word line WL1, becomes very small because most of the supplying voltage Vcc applied to the cell plate CP0_1 is applied to the storage node junction capacitor, in the memory cell CELL0, CELL1 connected to the word line WL0. However, the charge amount xcex94Q1 of the ferroelectric capacitor, in the memory cells CELL2, CELL3 connected to the word line WL1, is reduced, if the memory cells CELL0, CELL1 connected to the word line WL0 are derived repeatedly without driving the memory cells CELL2, CELL3 connected to the word line WL1, as shown in FIG. 6. Consequently, the voltage difference between VBL1 and the reference voltage Vref becomes small. In other words, the margin to distinguish the data xe2x80x9c1xe2x80x9d from the data xe2x80x9c0xe2x80x9d, is reduced to such a point that there exists a high probability for data disturbance.
It is, therefore, an object of the present invention to provide a FeRAM capable of preventing data disturbance through a cell plate that is shared by the adjacent memory cells.
It is, another object of the present invention to provide a FeRAM driving method capable of preventing the generation of a voltage difference between two electrodes of the capacitor by equalizing the voltage of the storage node in the memory cell, which is not driven, but is sharing the cell plate with the adjacent cell, which is driven.
In accordance with an aspect of the present invention, there is provided a FeRAM device having a first memory cell and a second memory cell sharing a cell plate, wherein the first memory cell and the second memory cell are commonly coupled to a bit line, and wherein the first memory cell is driven by a first word line and the second memory cell is driven by a second word line, the first memory cell comprising a first ferroelectric capacitor having a first electrode connected to the cell plate, a second electrode, and a ferroelectric layer disposed between the first electrode and the second electrode; a first transistor having a first gate electrode connected to the first word line, a first source and a first drain, wherein the first source and the first drain of the first transistor are respectively connected to the bit line and the second electrode of the first ferroelectric capacitor; and a second transistor having a second gate electrode connected to the second word line, a second source and a second drain, wherein the second source and the second drain of the second transistor are respectively connected to the second electrode of the first ferroelectric capacitor and the cell plate. The second memory cell comprises a second ferroelectric capacitor having the first electrode connected to the cell plate, a third electrode, and the ferroelectric layer disposed between the first electrode and the third electrode; a third transistor having a third gate electrode connected to second word line, a third source and a third drain, wherein the third source and the third drain of the third transistor are respectively connected to the bit line and the third electrode of the third ferroelectric capacitor; and a fourth transistor having a fourth gate electrode connected to the first word line, a fourth source and a fourth drain, wherein the fourth source and fourth drain of the fourth transistor are respectively connected to the third electrode of the second ferroelectric capacitor and the cell plate.
In accordance with still another aspect of the present invention, there is provided a FeRAM device having a first memory cell and a second memory cell sharing a cell plate line, wherein the first memory cell and the second memory cell are commonly coupled to a bit line, and wherein the first memory cell is driven by a first word line and the second memory cell is driven by a second word line, the device comprising a first dummy word line diverged from the first word line; and a second dummy word line diverged from the second word line.
In accordance with still another aspect of the present invention, there is provided a FeRAM device, comprising a first ferroelectric capacitor having a first having a first electrode connected to a cell plate, a ferroelectric layer, and a second electrode, a first memory cell and a second memory cell sharing the cell plate, wherein the first memory cell and the second memory cell are commonly coupled to a bit line, and wherein the first memory cell is driven by a first word line and the second memory cell is driven by a second word line; a semiconductor substrate; a first dummy word line diverged from the first word line; a second dummy word line diverged from the second word line; a first transistor having a first gate, a first source and a first drain, wherein the first gate electrode of the first transistor is formed on the semiconductor substrate and connected to the first word line, and wherein the first source and the first drain of the first transistor are respectively connected to the bit line and the second electrode of the first ferroelectric capacitor; a second transistor having a second gate electrode, a second source and a second drain, wherein the second gate electrode of the second transistor is formed on the semiconductor substrate and connected to the second word line, and wherein the second source and the second drain of the second transistor are respectively connected to the second electrode of the first ferroelectric capacitor and the cell plate; a third transistor having a third gate electrode, a third source and a third drain, wherein the third gate electrode is formed on the semiconductor substrate and connected to the second word line; and a fourth transistor having a fourth gate electrode, a fourth source and a fource drain, wherein the fourth gate electrode is connected to the first dummy word line. The FeRAM device further comprising a second ferroelectric capacitor having the first electrode connected to the cell plate, a third electrode, and the ferroelectric layer disposed between the first electrode and the third electrode, wherein the third source and the third drain of the third transistor are respectively connected to the bit line and the third electrode of the second ferroelectric capacitor; and wherein the source and the drain of the fourth transistor are respectively connected to the third electrode of the second ferroelectric capacitor and the cell plate. The ferroelectric capacitor is formed over the second transistor and the fourth transistor, and wherein one side of the first electrode is overlapped with a portion of the second transistor and a second side of the first electrode is overlapped with a portion of the fourth transistor.
In accordance with still another aspect of the present invention, there is provided a method for driving a FeRAM device including a first memory cell and a second memory cell sharing a cell plate line, said first memory cell having a first ferroelectric capacitor and said second memory cell having a second ferroelectric capacitor, of said second ferroelectric capacitor, the first ferroelectric capacitor and the second ferroelectric capacitor each including a first electrode connected to the cell plate, a ferroelectric layer and a second electrode, comprising steps of coupling the first memory cell and the second memory cell to a bit line; driving the first memory cell by a first word line and driving the second memory cell by a second word line; and maintaining an equal voltage of the first electrode of said second ferroelectric capacitor and the second electrode of said second ferroelectric capacitor while the first memory cell is driven.